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semiconducto r fedl9471-01 issue date: aug. 21, 2008 ML9471 1/3, 1/4, 1/5 duty 80 output lcd driver 1/20 general description the ML9471 is a lcd driver for dynamic display providing 3-duty-switchable pins (1/3, 1/4, 1/5 duty). it can directly drive lcds of up to 400, 320 and 240 segments when 1/5, 1/4 and 1/3 duty are selected respectively. features ? operating range supply voltage : 3.0 to 5.5 v operating temperature range : ? 40 to + 105 ? c ? segment output : 80 pins 1/5 duty : up to 400 segments can be displayed. 1/4 duty : up to 320 segments can be displayed. 1/3 duty : up to 240 segments can be displayed. ? serial transfer clock frequency : 4 mhz ? serical interface with cpu :through three input pins (data_in, load, and clock) ? built-in oscillator circuit for common signals ? one-to-one correspondence between input data and output data when input data is at ?h? level : display goes on. when input data is at ?l? level : display goes off. ? the entire display can be turned off. ( blank pin) ? package options 100-pin plastic tqfp (tqfp100-p-1414-0.50-k) (product name: ML9471tb)
fedl9471-01 lapis semiconductor ML9471 2/20 block diagram 80-dot segment driver 80-bit latch 5 80-bit latch 4 latch selector load osc 80 80-bit latch 3 80-bit latch 1 80-bit latch 2 data_in clock osc_out osc_out osc_in dsel1 dsel2 v dd gnd blank timing generator 80-ch data selector common driver seg1 seg80 v lc1 v lc2 v lc3 com1 com2 com3 com4 com5 80 80 80 80 80 88-stage shift register
fedl9471-01 lapis semiconductor ML9471 3/20 pin configuration (top view) 100-pin plastic tqfp 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 3 2 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 7 6 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 se g 50 se g 49 se g 48 se g 47 se g 46 s e g 45 se g 44 se g 43 se g 42 se g 41 se g 40 se g 39 seg 38 se g 37 se g 36 seg 35 seg 34 se g 33 se g 32 seg 31 nc v dd lo a d clo c k d a t a _ in b l a n k dse l2 dse l1 o s c _ o u t o sc _ o ut o sc _ in g nd v l c 3 v l c 2 v l c 1 co m5 co m4 co m3 co m2 co m1 se g 80 se g 7 9 se g 78 se g 77 se g 76 seg 75 seg 74 seg 73 seg 72 seg 71 seg 70 seg 69 seg 68 seg 67 seg 66 seg 65 seg 64 seg 63 seg 62 seg 61 seg 60 seg 59 seg 58 seg 57 seg 56 seg 55 seg 54 seg 53 seg 52 seg 51 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 30 seg 29 se g s eg seg 26 27 28
fedl9471-01 lapis semiconductor ML9471 4/20 pin description symbol type description osc_in osc_out osc_out i o o pins for oscillation. the oscillator circuit is configured by externally connecting two resistors and a capacitor. make the wiring length as short as possible, because the resistor connected to the osc_in pin has a higher value and the circuit is susceptible to external noise. data_in i serial data input pin. the display goes on when input data is at a ?h? level, and it goes off when input data is at ?l? level. clock i shift clock input pin. data from the data_in pin is transferred in synchronization with the rising edge of the shift clock. load i load signal input pin. serially input data is transferred to the 80-bit latch at ?h? level of this load signal, then held at ?l? level. blank l input pin that turns off all segments. the entire display goes off when ?l? level is applied to this pin. the display returns to the previous state when ?h? level is applied. dsel1 dsel2 i i input pins to select 1/3, 1/4, or 1/5 duty. following shows how each duty is selected. dsel2 dsel1 duty selected l l 1/3 l h 1/4 h x 1/5 x: don?t care com1 to com5 o display output pins for lcd. these pins are connected to the common side of the lcd panel. seg1 to seg80 o display output pins for lcd. theses pins are connected to the segment side of the lcd panel. for the correspondence between the output of these pins and input data, see the ?data structure? section. v lc1 , v lc2, v lc3 ? bias pins for lcd driver. through these pins, bias voltages for the lcd are externally supplied. the bias potential must meet the following condition: v dd > v lc1 ? v lc2 > v lc3 =gnd v dd , gnd ? supply voltage pin and ground pin. note: built-in schmitt circuit is used for all input pins.
fedl9471-01 lapis semiconductor ML9471 5/20 absolute maximum ratings parameter symbol condition rating unit supply voltage v dd ta = 25c ?0.3 to 6.5 v input voltage v i ta = 25c ?0.3 to v dd +0.3 v storage temperature t stg ? ?55 to 150 c power dissipation p d ta < 105c 700 mw output current i o ? ?2.0 to 2.0 ma recommended operating conditions parameter symbol condition range unit supply voltage v dd v lc3 = gnd 3.0 to 5.5 v clock frequency f cp ? 1 to 4 mhz operating temperature ta ? ?40 to 105 c oscillator circuit parameter symbol applicable pin condition min. max. unit oscillator resistance r 0 osc_out ? 20 120 k ? ? oscillator capacitance c 0 osc_out ? 0.00047 0.01 ? f current limiting resistance r 1 osc_in ? 62 360 k ? ? common signal frequency f com com1 to com5 ? 25 250 hz note: see section, ?reference data?, for the resistor and capacitor values in the table. rc values in oscillator circuit parameter symbol applicable pin 1/3 duty 1/4 duty 1/5 duty unit oscillator resistance r 0 osc_out 68 51 43 k ?? oscillator capacitance c 0 osc_out 0.001 0.001 0.001 ? f current limiting resistance r 1 osc_in 220 160 130 k ?? example of an oscillator circuit:
fedl9471-01 lapis semiconductor ML9471 6/20 electrical characteristics dc characteristics (v dd = 3.0 to 5.5 v, ta = ?40 to +105c, unless otherwise specified) parameter symbol applicable pin condition min. max. unit ?h? input voltage 1 v ih1 clock, osc_in ? 0.85 v dd v dd v ?l? input voltage 1 v il1 clock, osc_in ? gnd 0.15 v dd v ?h? input voltage 2 v ih2 *1 ? 0.8 v dd v dd v ?l? input voltage 2 v il2 *1 ? gnd 0.2 v dd v ?h? input current i ih all input pins v dd = 5.5 v, v i = v dd ? 10 ? a ? ?l? input current i il all input pins v dd = 5.5 v, v i = 0 v ? 10 ? ? a ? v oc0a i o = ? 100 ? a v dd ? 1 ? v v oc1 i o = ? 100 ? a *3 v lc1 ? 1 v lc1 +1 v v oc2 i o = ? 100 ? a *4 v lc2 ? 1 v lc2 +1 v common output voltage v oc3 com1 - com5 v dd = 3.0 v i o = +100 ? a *5 ? v lc3 +1 v v os0 i o = ? 10 ? a v dd ? 1 ? v v os1 i o = ? 10 ? a *3 v lc1 ? 1 v lc1 +1 v v os2 i o = ? 10 ? a *4 v lc2 ? 1 v lc2 +1 v segment output voltage v os3 seg 1 - seg 80, v dd = 3.0 v i o = +10 ? a *5 ? v lc3 +1 v supply current i dd v dd v dd = 5.0 v, no load. *2 ? 0.5 ma *1 applies to all input pins excluding clock and osc_in. *2 r 0 = 51 k ? r 1 = 160 k ? c 0 = 0.001 ? f *3 v lc1 = 2.0v *4 v lc2 = 1.0v *5 v lc3 = 0v
fedl9471-01 lapis semiconductor ML9471 7/20 ac characteristics (v dd =3.0 to 5.5v, ta = ?40 to +105c, unless otherwise specified) parameter symbol condition min. typ. max. unit clock ?h? time t whc ? 70 ? ? ns clock ?l? time t wlc ? 70 ? ? ns data set-up time t ds ? 50 ? ? ns data hold time t dh ? 50 ? ? ns load ?h? time t whl ? 100 ? ? ns clock-to-load time t cl ? 100 ? ? ns load-to-clock time t lc ? 100 ? ? ns clock rise time, fall time t r1 , t f1 ? ? ? 50 ns osc_in input frequency f osc ? ? ? 20 khz osc_in ?h? time t who ? 20 ? ? ? s osc_in ?l? time t wlo ? 20 ? ? ? s osc_in rise time, fall time t r2 , t f2 ? ? ? 100 ns
fedl9471-01 lapis semiconductor ML9471 8/20 power-on/off timing * v lc1 , v lc2 are applied when v dd is applied to external bias resistor. initial signal timing * once v dd is applied, blank should be applied to ?l? level to make all segments off until first group of display data is latched. v dd blank
fedl9471-01 lapis semiconductor ML9471 9/20 functional description operation as sh own in ?data structure?, the display data consists of the data field corresponding to the output for turning the segments on or off and the select field that selects field that selects the input block of data. data input to the data_in pin is loaded into the 88-bit shift register, transferred to the 80-bit latch while the load signal is at ?h? level, and then output via the 80-dot segment driver. data structure in put data correspondence between select bits and com1 to com5 c5 c4 c3 c2 c1 description 0 0 0 0 1 display data corresponding to com1 0 0 0 1 0 display data corresponding to com2 0 0 1 0 0 display data corresponding to com3 0 1 0 0 0 display data corresponding to com4 1 0 0 0 0 display data corresponding to com5 notes: 1. arbitrary data can be set for the dummy bits. 2. select bit, c 1 to c 5 , selects 80-bit latches that correspond to com1 to com5, respectively. therefore, if ?1? is set for more than one select bit, data is set to all the corresponding 80-bit latches. example: if ?1? is set to all the select bits c 1 to c 5 , the display data of d 1 to d 80 is set to all the 80-bit latches that correspond to com1 to com5.
fedl9471-01 lapis semiconductor ML9471 10/20 com1 ? com5 timing chart: v dd v lc1 v lc2 v lc3 com1 com2 com3 1/3 duty com timing v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3
fedl9471-01 lapis semiconductor ML9471 11/20 segn true value table: latch1 latch2 latch3 latch4 latch5 com1 com2 com3 com4 com5 segn ?h? ?m2? ?m2? ?m2? ?m2? ?m1? ?l? ?m1? ?m1? ?m1? ?m1? ?m2? ?m2? ?h? ?m2? ?m2? ?m2? ?m1? ?m1? ?l? ?m1? ?m1? ?m1? ?m2? ?m2? ?m2? ?h? ?m2? ?m2? ?m1? ?m1? ?m1? ?l? ?m1? ?m1? ?m2? ?m2? ?m2? ?m2? ?h? ?m2? ?m1? ?m1? ?m1? ?m1? ?l? ?m1? ?m2? ?m2? ?m2? ?m2? ?m2? ?h? ?l? 0 0 0 0 1 ?m1? ?m1? ?m1? ?m1? ?l? ?h? *note: ?h? = v dd ; ?m1? = v lc1 ; ?m2? = v lc2 ; ?l? = v lc3 =gnd
fedl9471-01 lapis semiconductor ML9471 12/20 timing chart for 1/3 duty drive mode:
fedl9471-01 lapis semiconductor ML9471 13/20 timing chart for 1/4 duty drive mode: v dd v lc1 v lc2 v lc3 com1 com2 com3 com4 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 seg1 seg2 com1 com2 com3 com4
fedl9471-01 lapis semiconductor ML9471 14/20 timing chart for 1/5 duty drive mode: v dd v lc1 v lc2 v lc3 com1 com2 com3 com4 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 v dd v lc1 v lc2 v lc3 seg1 seg2 com1 com2 com3 com4 seg1 seg2 com5 com5 v dd v lc1 v lc2 v lc3
fedl9471-01 lapis semiconductor ML9471 15/20 application circuits (for 1/4 duty)
fedl9471-01 lapis semiconductor ML9471 16/20 reference data the data shown in this section is for reference (a metal film resistor and a film capacitor are used). resistor and capacitor values must be determined based on experiments. use the following expression to convert oscillation frequency to common frame frequency (or vice versa): f com =f osc duty/16 f com : common frame frequency f osc : oscillation frequency duty : e.g., 1/4 for 1/4 duty for example, if f com =100hz at 1/5 duty, the oscillation frequency is f osc =8000hz. i dd vs. v dd 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 55.5 6 6.5 v dd [v] i dd [ma] ta=25c r0=51k ? r1=160k ? c0=0.001f 1/4 duty
fedl9471-01 lapis semiconductor ML9471 17/20 fosc---r0,c0 ML9471 oscillator frequency result vdd=3v 25c 0.10 1.00 10.00 100.00 0 25 50 75 100 125 150 r0[k ? ] fosc[khz] 0.00047f | 62k ? 0.00047f | 360k ? 0.01f | 62k ? 0.01f | 360k ? ML9471 oscillator frequency result vdd=5.5v 25c 0.10 1.00 10.00 100.00 0 25 50 75 100 125 150 r0[k ? ] fosc[khz] 0.00047f | 62k ? 0.00047f | 360k ? 0.01f | 62k ? 0.01f | 360k ?
fedl9471-01 lapis semiconductor ML9471 18/20 package dimensions tqfp100-p-1414-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy lead finish sn-2bi (bi 2% typ.) pin treatment solder plating ( t 5 m) package weight (g) 0.55 typ. 5 rev. no./last revised 1/jul. 18, 2007 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl9471-01 lapis semiconductor ML9471 19/20 revision history page document no. date previous edition current edition description pedl9471-01 dec. 15, 2006 ? ? preliminary edition 1 pedl9471-02 jan. 15, 2007 ? ? preliminary edition 2 pedl9471-03 jan. 9, 2008 ? ? preliminary edition 3 fedl9471-01 aug. 21, 2008 ? ? final edition 1
fedl9471-01 lapis semiconductor ML9471 20/20 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (suc h as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2008 - 2011 lapis semiconductor co., ltd.

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